View TSPC2605VG66_7755818.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/36 may 1998 tspc2605 integrated secondary cache module for powerpc microprocessors description the tspc2605 is a single chip, 256kb integrated lookaside cache with copyback capability designed for powerpc applications (tspc603e). using 0.38 m m technology along with standard cell logic technology, the tspc2605 integrates data, tag, host interface, and least recently used (lru) memory with a cache controller to provide a 256kb, 512kb, or 1 mb level 2 cache with one, two, or four chips on a 64bit powerpc bus. main features single chip l2 cache for powerpc 66 mhz zero wait state performance (2111 burst) fourway set associative cache design 32k x 72 data memory array 8k x 18 tag array address parity support lru cache control logic copyback or writethrough modes of operation copyback buffer for improved performance single 3.3 v power supply 5 v tolerant i/o 1, 2, or 4 chip cache solution (256kb, 512kb, or 1mb) single clock operation compliant with ieee standard 1149.1 test access port (jtag) supports up to 4 processors in a shared cache configuration screening / quality / packaging this product is manufactured in full compliance with : mil-std-883 class b or according to tcs standards upscreening based upon tcs standards full military temperature range (t c = -55 c, tc = +125 c) industrial temperature range (t c = 40 c, t c = +110 c) power supply = 3.3 v 5 %. 241pin pbga and cbga packages pbga 241 zp suffix plastic ball grid array cbga 241 g suffix ceramic ball grid array (to be introduced)
tspc2605 2/36 summary a. general description 3 . . . . . . . . . . . . . . 1. pin assignment 3 . . . . . . . . . . . . . . . . . . . . . . . . . . 2. signal description 4 . . . . . . . . . . . . . . . . . . . . . 3. simplified block diagram 6 . . . . . . . . . . . . . . b. detailed specifications 7 . . . . . . . . . . . 1. scope 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. applicable documents 7 . . . . . . . . . . . . . . . . . 3. requirements 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1. general 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2. design and construction 7 . . . . . . . . . . . . . . . . . 3.2.1.terminal connections 7 . . . . . . . . . . . . . . . . . 3.2.2.lead material and finish 7 . . . . . . . . . . . . . . . 3.2.3.hermetic package 7 . . . . . . . . . . . . . . . . . . . . 3.3. absolute maximum ratings 7 . . . . . . . . . . . . . . . 3.4. thermal characteristics 7 . . . . . . . . . . . . . . . . . 3.4.1.pbga package 7 . . . . . . . . . . . . . . . . . . . . . . 3.4.2.cbga package 8 . . . . . . . . . . . . . . . . . . . . . . 3.5. marking 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4. electrical characteristics 9 . . . . . . . . . . . 4.1. recommanded operating conditions 9 . . . . . . 4.2. dc characteristics 9 . . . . . . . . . . . . . . . . . . . . . . 4.3. capacitance 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4. ac operating conditions 10 . . . . . . . . . . . . . . . 4.4.1.ac clock specification 10 . . . . . . . . . . . . . . . . 4.4.2.ac specifications 10 . . . . . . . . . . . . . . . . . . . . 4.4.3.response to 60x transfer attributes 11 . . . . 4.4.4.response to chipset transfer attributes 11 . 4.4.5.transfer attributes for l2 copyback 11 . . . 4.5. jtag ac operating conditions 12 . . . . . . . . . . 4.5.1.tap controller timing 12 . . . . . . . . . . . . . . . . . 5. functional description 13 . . . . . . . . . . . . . . . 5.1. system usage and requirments 13 . . . . . . . . . 5.1.1.comprehension of l2 claim 13 . . . . . . . . . . 5.1.2.pipeline depth 13 . . . . . . . . . . . . . . . . . . . . . . . 5.1.3.bus mastering 13 . . . . . . . . . . . . . . . . . . . . . . . 5.2. configuration pins 13 . . . . . . . . . . . . . . . . . . . . . 5.2.1.cfg0 cfg2 13 . . . . . . . . . . . . . . . . . . . . . . . 5.2.2.cfg3 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3.cfg4 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3. reset/initialization 14 . . . . . . . . . . . . . . . . . . . . . 5.4. 60x bus operation 14 . . . . . . . . . . . . . . . . . . . . . 5.4.1.address tenures 14 . . . . . . . . . . . . . . . . . . . . . 5.4.2.data tenures 15 . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3.data streaming 15 . . . . . . . . . . . . . . . . . . . . . . 5.4.4.data bus parking 15 . . . . . . . . . . . . . . . . . . . . 5.4.5.processor reads 15 . . . . . . . . . . . . . . . . . . . . . 5.4.6.processor writes 16 . . . . . . . . . . . . . . . . . . . . . 5.4.7.transaction pipelining 16 . . . . . . . . . . . . . . . . 5.5. memory coherence 16 . . . . . . . . . . . . . . . . . . . . 5.5.1.snoop reads 16 . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2.snoop writes 16 . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3.snoop kills 16 . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6. two/four chip implementation 17 . . . . . . . . . . 5.6.1.multiple castouts 17 . . . . . . . . . . . . . . . . . . . . . 5.6.2.snoop hit before castout 17 . . . . . . . . . . . . . 5.7. multiprocessing 17 . . . . . . . . . . . . . . . . . . . . . . . . 5.8. poweringdown 17 . . . . . . . . . . . . . . . . . . . . . . . 5.9. asynchronous signals 17 . . . . . . . . . . . . . . . . . . 5.9.1.l2 flush 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9.2.l2 miss inh 18 . . . . . . . . . . . . . . . . . . . . . . . . 5.9.3.l2 tag clr 18 . . . . . . . . . . . . . . . . . . . . . . . . . 5.9.4.l2 update inh 18 . . . . . . . . . . . . . . . . . . . . . 5.10. waveforms 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11. test access port description 28 . . . . . . . . . . . . 5.11.1.instruction set 28 . . . . . . . . . . . . . . . . . . . . . . 5.11.2.standard instructions 28 . . . . . . . . . . . . . . . . 5.11.3.sample/preload tap instruction 28 . . . 5.11.4.extest tap instruction 28 . . . . . . . . . . . . . 5.11.5.clamp tap instruction 28 . . . . . . . . . . . . . . 5.11.6.highz tap instruction 28 . . . . . . . . . . . . . . . 5.11.7.bypass tap instruction 28 . . . . . . . . . . . . . 5.11.8.disabling the tap and boundary scan 29 . 5.12.boundary scan order 30 . . . . . . . . . . . . . . . . . . 5.12.1.bit number 30 . . . . . . . . . . . . . . . . . . . . . . . . . 5.12.2.bit/pin name 30 . . . . . . . . . . . . . . . . . . . . . . . . 5.12.3.bit/pin type 30 . . . . . . . . . . . . . . . . . . . . . . . . . 5.12.4.output enable 30 . . . . . . . . . . . . . . . . . . . . . . 6. preparation for delivery 33 . . . . . . . . . . . . . 6.1. packaging 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2. certificate of compliance 33 . . . . . . . . . . . . . . . . 7. handling 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8. package mechanical data 34 . . . . . . . . . . . . 8.1. 241 pins pbga 34 . . . . . . . . . . . . . . . . . . . . . . 8.2. 241 pins cbga 35 . . . . . . . . . . . . . . . . . . . . . . 9. ordering information 36 . . . . . . . . . . . . . . . .
tspc2605 3/36 a. general description 1. pin assignment 8 5 4 3 2 19 b c g a d e f h j dh21 abb dh19 dh29 cpu3 br cpu3 dbg dp2 dp3 cfg1 l2 dbg dh28 v ss v dd dh4 cfg0 dbb ci aac k ta dp0 dh6 dl13 dl29 dl30 dl31 v ss v ss v dd fdn cpu3 bg cfg4 l2 miss inh k l m n p r v w dh27 dh30 hreset 67 dh17 dh22 dh16 v ss v ss cpu br wt dh31 dh18 tea pwrdn v dd v dd t u cpu2 dbg artry 17 14 13 12 11 10 18 dl24 dl16 dl19 dp6 dl18 dl21 v ss ap3 tt2 l2 tag clr trst cpu bg dp7 ap2 l2 flush tt 3 a1 a15 tsiz0 apen v ss tdo tdi sreset tt4 tt0 tck a14 tsiz1 v ss cfg3 v ss dh24 dh25 dl17 dl20 dl23 dl22 dh26 tt1 a0 15 16 dl25 v dd cpu4 dbg dl28 v dd ap0 clk dl27 dl26 cpu4 br ts v dd a3 a5 nc tms tbst l2 update inh v dd cpu4 bg 19 ape ap1 l2 ci a2 a16 tsiz2 gbl a13 a4 a6 v dd v dd v ss v ss v ss v ss v ss v ss v dd v dd v ss v dd a18 a19 a17 v dd v ss v dd v ss v dd v ss v dd a22 a20 a21 v dd cfg2 v d d v dd v ss v dd v ss v ss a24 a25 a23 v dd v dd v dd v ss v ss v dd v ss a27 a28 a26 v ss v dd v ss v dd v ss v dd v ss a30 a31 a29 a11 a10 a12 a8 a7 a9 l2 bg v ss v ss v dd v dd v dd v ss v ss cpu2 bg dh5 l2 claim dh20 dh23 cpu2 br l2 br cpu dbg nc v dd v ss v ss v ss dh14 dh10 dl1 dl4 v ss v ss v ss v dd dl15 dh1 dp1 dh13 dh11 dl0 dl3 dl6 dp4 dl10 dl12 dl14 dh7 dh3 dh0 dh15 dh12 dh9 dh8 dl2 dl5 dl7 dl8 dl9 dl11 dh2 dp5 top view (xray view) v ss v ss
tspc2605 4/36 2. signal description pin locations pin name type description 19g, 17h 19h, 17j 19j, 17k 19k, 17l 19l,17m 19m, 17n 19n,17p 19p, 17r 19r,18t, 19t, 18u, 19u,18v, 19v, 18w * a0 a31 i/o address inputs from processor. can also be outputs for processor snoop addresses. a0 is the msb. a31 is the lsb. 3g aack i/o address acknowledge input/output. 2a abb i/o used as an input to qualify bus grants. driven as an output during address tenure initiated by the tspc2605. 17c 19c, 17d * ap0 ap3 i/o address parity. 19b ape o address parity error. when an address parity error is detected, ape will be driven low one clock cycle after the assertion of ts then highz following clock cycle. 18e apen i address parity enable. when tied low, enables address parity bits and the address parity error bit. 1g artry i/o address retry status i/o. generated when a read or write snoop to a dirty processor cache line has occurred. 2u 2v 1v 17e 2b cfg0 cfg1 cfg2 cfg3 cfg4 i configuration inputs. these must be tied to either v dd or v ss . cfg0 cfg1 cfg2 0 0 0 256kb 0 1 0 512kb; a26 = 0 0 1 1 512kb; a26 = 1 1 0 0 1mb; a25 a26 = 00 1 0 1 1mb; a25 a26 = 01 1 1 0 1mb; a25 a26 = 10 1 1 1 1mb; a25 a26 = 11 cfg3 snoop data tenure selector 0 supports snoop data tenure 1 does not support snoop data tenure cfg4 aack driver enable 0 disable aack driver 1 enable aack driver 2g ci i/o cache inhibit i/o. 3m clk i clock input. this must be the same as the processor clock input. 2m cpu bg i cpu bus grant input. 3e cpu2 bg i tspc2605 logically ors this signal with cpu bg . used in multiprocessor configuration as the second cpu bg . 1b cpu3 bg i tspc2605 logically ors this signal with cpu bg . used in multiprocessor configuration as the third cpu bg . 1t cpu4 bg i tspc2605 logically ors this signal with cpu bg . used in multiprocessor configuration as the fourth cpu bg . 2h cpu br i cpu bus request input. 2d cpu2 br i tspc2605 logically ors this signal with cpu br . used in multiprocessor configuration as the second cpu br . 2c cpu3 br i tspc2605 logically ors this signal with cpu br . used in multiprocessor configuration as the third cpu br . 1u cpu4 br i tspc2605 logically ors this signal with cpu br . used in multiprocessor configuration as the fourth cpu br . 1f cpu dbg i cpu data bus grant input from arbiter. 3d cpu2 dbg i tspc2605 logically ors this signal with cpu dbg . used in multiprocessor configuration as the second cpu dbg . 3c cpu3 dbg i tspc2605 logically ors this signal with cpu dbg . used in multiprocessor configuration as the third cpu dbg . * see pin diagram (page 2) for specific pin assignment of these bus signals.
tspc2605 5/36 pin locations pin name type description 2t cpu4 dbg i tspc2605 logically ors this signal with cpu dbg . used in multiprocessor configuration as the fourth cpu dbg . 11a 13a, 15a 18a,11b 17b, 11c, 12c, 10u,11u, 10v 12v, 14v 17v, 11w 17w * dl0 dl31 i/o data bus low input and output. dl0 is the msb. dl31 is the lsb. 4a 10a, 4b 10b, 6c,10c, 8u, 9u, 3v 6v,8v, 9v, 3w 10w * dh0 dh31 i/o data bus high input and output. dh0 is the msb. dh31 is the lsb. 2j dbb i/o data bus busy. used as input when processor is master, driven as an output after a qualified l2 dbg when tspc2605 is the bus master. note: to operate in fast l2 mode, this pin must be tied high. 14a, 18b, 5c, 8c,16u, 7v, 13v, 2w * dp0 dp7 i/o data bus parity input and output. 1c fdn i/o flush done i/o used for communication between other tspc2605 devices. must be tied together between all tspc2605 parts along with a pullup resistor. 19e gbl o global transaction. always negated when mpc2604 is bus master. 1j hreset i hard reset input from processor bus. this is an asynchronous input that must be low for at least 16 clock cycles to ensure the tspc2605 is properly reset. for proper initialization, trst must be asserted before hreset is asserted. 3a l2 bg i bus grant input from arbiter. 1d l2 br i/o bus request i/o. normally used as an output. 19d l2 ci i secondary cache inhibit sampled, after assertion of ts . assertion prevents linefill. 2f l2 claim o l2 cache claim output. used to claim the bus for processor initiated memory operations that hit the l2 cache. l2 claim goes true (low) before the rising edge of clk following ts true. because this output is not always driven, a pullup resistor may be necessary to ensure proper system functioning. 2e l2 dbg i data bus grant input. comes from system arbiter, used to start data tenure for bus operations where tspc2605 is the bus master. 18d l2 flush i causes cache to write back dirty lines and clears all tag valid bits. 3b l2 miss inh i prevents line fills on misses when asserted. 2n l2 tag clr i invalidates all tags and holds cache in a reset condition. 3n l2 update inh i cache disable. when asserted, the tspc2605 will not respond to signals on the local bus and internal states do not change. 3j pwrdn i provides low power mode. prevents address and data transitions into the ram array. tspc2605 becomes active 4 m s after deassertion. clock must be externally disabled. 1n sreset i soft reset input from processor bus. 1e ta i/o transfer acknowledge status i/o from processor bus. 3k tbst i/o transfer burst status i/o from processor bus. used to distinguish between burstable and nonburstable memory operations. 2p tck i test clock input for ieee 1149.1 boundary scan (jtag). 1p tdi i test data input for ieee 1149.1 boundary scan (jtag). 1r tdo o test data output for ieee 1149.1 boundary scan (jtag). 1h tea i transfer error acknowledge status input from processor bus. 3p tms i test mode select for ieee 1149.1 boundary scan (jtag). * see pin diagram (page 2) for specific pin assignment of these bus signals.
tspc2605 6/36 pin locations pin name type description 2r trst i test reset input for ieee 1149.1 boundary scan (jtag). if jtag will not be used, trst should be tied low. 3l ts i/o transfer start i/o from processor bus (can also come from any bus master on the processor bus). signals the start of either a processor or bus master cycle. 17f 19f * tsiz0 tsiz2 i/o transfer size i/o from processor bus. 1k, 2k, 1l, 2l, 1m * tt0 tt4 i/o transfer type i/o from processor bus. 3h wt i/o write through status input from processor bus. when tied to ground, the tspc2605 will operate in writethrough mode only (no copyback). 4c, 15c, 16c, 9d 11d,8h 10h, 4j, 8j, 9j, 16j, 4k, 8k, 12k, 16k, 4l, 11l, 12l, 16l, 10m 12m, 3t, 9t 11t, 17t, 3u, 4u, 15u, 17u v dd supply power supply: 3.3 v 5%. 7c, 9c, 13c, 14c, 7d, 8d, 12d, 13d, 4g, 16g 18g, 4h, 11h, 12h, 16h, 10j 12j, 9k 11k, 8l 10l, 4m, 8m, 9m, 16m, 4n, 16n, 7t, 8t, 12t, 13t, 5u 7u, 12u 14u v ss supply ground. 3f, 3r nc e no connection: there is no connection to the chip. * see pin diagram (page 2) for specific pin assignment of these bus signals. 3. simplified block diagram way select dh0 dh31 dl0 dl31 dp0 dp7 rd/wr a27, a28 a0 a31 60x bus interface rd/wr control controller and bus interface 8k x 72 x 4 data ram copyback buffer 2k x 8 lru 2k x 18 x 4 tag ram compare
tspc2605 7/36 b. detailed specifications 1. scope this drawing describes the specific requirements for the microprocessor tspc2605, in compliance with mil-std-883 class b or tcs standard screening. 2. applicable documents 1) mil-std-883 : test methods and procedures for electronics. 2) mil-prf-38535 appendix a : general specifications for microcircuits. 3. requirements 3.1. general the microcircuits are in accordance with the applicable documents and as specified herein. 3.2. design and construction 3.2.1.terminal connections depending on the package, the terminal connections shall be is shown in a.1 pin assignment. 3.2.2.lead material and finish lead material and finish shall be as specified in mil-std-1835 (see enclosed 8) 3.2.3.hermetic package the macrocircuits are packaged in 241 pin ceramic and plastic ball grid array packages (see 8.1 and 8.2) the precise case outlines are described at the end of the specification ( 8.1 and 8.2) and into mil-std-1835. 3.3. absolute maximum ratings rating symbol value unit power supply voltage v dd 0.5 to + 4.6 v voltage relative to v ss v in , v out 0.5 to v dd + 0.5 v output current (per i/o) i out 20 ma power dissipation (note 2) p d e w temperature under bias t bias 10 to + 85 c operating temperature t c 55 to +125 c storage temperature t stg 55 to +125 c notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommend operating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. power dissipation capability is dependent upon package characteristics and use envi- ronment. see package thermal characteristics. this device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this highimpedance circuit. this bicmos memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established.
tspc2605 8/36 3.4. thermal characteristics 3.4.1.pbga package rating symbol max unit thermal resistance junction to ambient (still air, test board with two internal planes) r q ja 26.5 c/w thermal resistance junction to ambient (200 lfpm, test board with two internal planes) r q ja 23.2 c/w thermal resistance junction to board (bottom) r q jb 15.9 c/w thermal resistance junction to case (top) r q jc 6.6 c/w 3.4.2.cbga package rating symbol max unit thermal resistance junction to ambient (still air, test board with two internal planes) r q ja tbd c/w thermal resistance junction to ambient (200 lfpm, test board with two internal planes) r q ja tbd c/w thermal resistance junction to board (bottom) r q jb tbd c/w thermal resistance junction to case (top) r q jc tbd c/w 3.5. marking the document where are defined the marking are identified in the related reference documents. each microcircuit are legible and permanently marked with the following information as minimum : - thomson logo, - manufacturer's part number, - class b identification if applicable, - date-code of inspection lot, - esd identifier if available, - country of manufacturing.
tspc2605 9/36 4. electrical characteristics 4.1. recommanded operating conditions parameter symbol min typ max unit supply voltage (operating voltage range) v dd 3.135 3.3 3.465 v input high voltage v ih 2.0 e 5.5 v input low voltage v il 0.5* e 0.8 v *v il (min) = 2.0 v ac (pulse width 20 ns). 4.2. dc characteristics parameter symbol min max unit input leakage current (all inputs, v in = 0 to v dd ) i lkg(i) e 1.0 m a output leakage current (highz state, v out = 0 to v dd ) i lkg(o) e 1.0 m a ac supply current (i out = 0 ma, all inputs = v il or v ih , v il = 0 v, and v ih 3.0 v, cycle time = 15 ns, max value assumes a constant burst read hit, with 100% bus utilization, and 100% hit rate) i cca e 720 ma ac quiescent current (i out = 0 ma, all inputs = v il or v ih , v il = 0 v and v ih 3.0 v, cycle time = 15 ns, all other inputs dc) i q e 195 ma output low voltage (i ol = + 8.0 ma) v ol e 0.4 v output high voltage (i oh = 4.0 ma) v oh 2.4 e v 4.3. capacitance parameter symbol typ max unit input capacitance c in 4 6 pf output capacitance c out 6 8 pf input/output capacitance c i/o 8 10 pf * f = 1.0 mhz, dv = 3.0 v, t a = 25 c, periodically sampled rather than 100% tested
tspc2605 10/36 4.4. ac operating conditions and characteristics (t c = 55 to +125 c, unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 2 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output measurement timing level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . output load 50 w termination to 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1.ac clock specification timin g tspc260566 parameter timing reference min max unit notes frequency of operation e 66.67 mhz clock cycle time 15 e ns clock rise and fall time , 1.0 2.0 ns 1, 2 clock duty cycle measured at 1.5 v 40 60 % clock shortterm jitter (cycle to cycle) e 150 ps 1 notes: 1. this parameter is sampled and not 100% tested. 2. rise and fall times for the clock input are measured from 0.4 to 2.4 v. v i h v i l v m vm = midpoint voltage (1.5 v) clock input timing diagram 4.4.2.ac specifications timin g tspc260566 parameter timing reference min max unit notes clock cycle time 15 e ns input setup time 4.5 e ns 1 clock to input invalid (input hold) 2 e ns 1 clock to output driven 2 9 ns 2 clock to output valid 2 9 ns clock to output invalid 2 e ns 2 clock to output highz 2 12 ns 2 pwrdn disable to recovery e 4 m s 2 notes: 1. all input specifications are measured from the ttl level (0.8 or 2.0 v) of the signal in question to the 1.4 v level of the r ising edge of the input clock. both input and output timings are measured at the pin. 2. this parameter is sampled and not 100% tested. clk inputs outputs
tspc2605 11/36 4.4.3.tspc2605 response to 60x transfer attributes tt0 tt4 tbst ci wt tag status tspc2605 response notes x1x10 0 1 x miss linefill (processor read miss) 1, 2, 3 x1x10 0 1 x hit l2 claim , aack , ta (processor read hit) 4 x1010 1 0 x hit clean paradox e invalidate the line (processor ncacheable read hit clean line) x1010 1 0 x hit dirty paradox e artry , l2 br , then write back data, invalidate the line (processor ncacheable read hit dirty line) 00110 0 1 x miss linefill except right after a snoop hit to processor (processor write miss) 1, 3, 5, 6 00110 0 1 1 hit l2 claim , aack , ta except after a snoop hit to processor (processor write hit) 5, 6 00x10 x 1 0 hit clean cache update (processor write through wt hit clean) 00110 0 1 0 hit dirty cache update, clear dirty bit 00010 1 1 0 hit dirty paradox e artry , l2 br , write back data, keep valid, clear dirty bit x0010 1 0 x hit clean paradox e invalidate the line (processor ncacheable write hit clean line) x0010 1 0 x hit dirty paradox e artry , l2 br , then write back data, invalidate the line (processor ncacheable sb write hit dirty line) 00100 x x x hit clean invalidate tag (flush block addressonly) 00100 x x x hit dirty artry , l2 br , write back data, invalidate tag (flush block addressonly) 00000 x x x hit clean no action (clean block addressonly) 00000 x x x hit dirty artry , l2 br , write back data, reset dirty bit (clean block addressonly) 01100 x x x hit invalidate tag (kill block addressonly) notes: 1. if a line fill is going to replace a dirty line and the cast out buffer (cob) is full, the line fill will be cancelled. (unle ss the line fill is a write which hits in the cob. in this case, the line fill will occur.) 2. if a burst read misses the cache but hits the cob, the tspc2605 will supply the data from the cob, but not perform a line fil l. 3. if artry is asserted during a line fill to replace a dirty line, the line fill will be cancelled, the tobereplaced line will recover its old tag (valid, dirty, tag field), and the cob goes back to an invalid condition, even if the line fill is a burst write to the line in the cob . 4. if artry is asserted during a read hit, the tspc2605 will abort the process. 5. if a processor burst write occurs right after a snoop write that was a cache hit, the tspc2605 will invalidate the line. if t he snoop was a cache miss, the tspc2605 will not perform a write allocate. 6. if a processor burst write occurs right after a snoop read that was a cache hit, the tspc2605 will update the cache and clear the dirty bit. if the snoop was a cache miss, the tspc2605 will perform a write allocate. 4.4.4.tspc2605 response to chipset transfer attributes tt0 tt4 tag status tspc2605 response 00100 x0010 x1110 hit clean invalidate line 00100 x0010 x1110 hit dirty artry and l2 br write back data, invalidate line (see note) 00000 x1010 hit clean no action 00000 x1010 hit dirty artry and l2 br , write back data, reset dirty bit (see note) 0110x 00110 hit invalidate (kill block) note: in all snoop push cases, br is sampled the cycle after the artry window. if br is asserted in this cycle, l2 br will be immediately negated and an assertion of l2 bg will be ignored. 4.4.5.transfer attributes generated for l2 copyback tt0 tt4 tbst ci wt 00010 0 1 1
tspc2605 12/36 4.5. jtag ac operating conditions and characteristics for the test access port (ieee 1149.1) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 3 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output measurement timing level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . output load 50 w termination to 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1.tap controller timing tspc260566 parameter symbol min max unit notes cycle time t ck 30 e ns clock high time t ckh 12 e ns 1 clock low time t ckl 12 e ns 1 clock low to output valid t a 5 9 ns clock low to output highz t ckz 0 9 ns 2 clock low to output active t ckx 0 9 ns 3, 4 setup times: tms tdi t s t sd 2 e ns 1 hold times: tms tdi t h t hd 2 e ns 1 notes: 1. this parameter is sampled and not 100% tested. 2. tdo will highz from a clock low edge depending on the current state of the tap state machine. 3. tdo is active only in the shiftir and shiftdr state of the tap state machine. 4. transition is measured 500 mv from steadystate voltage. this parameter is sampled and not 100% tested. tdi test data in tck test clock t ck tdo test data out t h t ckx t sd t s t hd t a t ckz tms test mode select t ck h t ck l figure 1. tap controller timing
tspc2605 13/36 5. functional description 5.1. system usage and requirements the tspc2605 is a highperformance lookaside cache for powerpc systems. a lookaside cache is defined as a cache that resides on the same bus as the processor, the memory controller, the dma bridge, and the arbiter. the advantage of a lookaside cache is that, when the processor makes a memory request, the cache adds no delay to the memory controller's response time in t he event that the request cannot be satisfied by the cache. however, there are certain system requirements that must be met before a lookaside cache can be used. 5.1.1.comprehension of l2 claim because the memory controller sees every memory request that is issued by the processor, there must be a mechanism for the cach e to inform the memory controller that it has detected a cache hit and that it will satisfy the processor's request. the tspc2605 has a signal calledl2 claim that is asserted whenever a cache hit is detected. any memory controller with which the tspc2605 is to be used must have the ability to monitor this signal. 5.1.2.pipeline depth the 60x bus allows pipelining of transactions such that a new transaction can be initiated before a previous transaction has fu lly completed. the level of pipelining that exists on the bus is defined by how many new data transactions have been initiated whil e the original transaction is still being processed. by this definition the tspc2605 can only work in a one level deep pipeline. in t he pres- ence of transactions for which it has asserted l2 claim , the tspc2605 can control the level of pipelining by delaying its assertion of aack . however, for transactions that it cannot control, the tspc2605 is dependent upon the memory controller to control pipeline depth. thus, another system requirement for the use of the tspc2605 is the use of a memory controller that only allows one leve l deep of pipelining on the 60x bus. 5.1.3.bus mastering bus mastering is a requirement only for systems which seek to use the tspc2605 as a copyback, as opposed to a writethrough, cache. the requirement is that the system arbiter must have the ability to allow the tspc2605 to become a bus master. specifica lly, the system arbiter must be able to recognize assertions of l2 br and must have the ability to assert l2 bg and l2 dbg . these are the only requirements above and beyond what should already exist in a powerpc system. all other necessary control signals are signals that are required for the processor to communicate with the memory controller, the dma bridge, and the arbi ter. 5.2. configuration pins the tspc2605 has five configuration pins: cfg0, cfg1, cfg2, cfg3, and cfg4. 5.2.1.cfg0 cfg2 these three configuration pins are used to implement the different cache sizes supported by the tspc2605. 256kb: for a single chip implementation, cfg0, cfg1, and cfg2 should all be tied low. 512kb: this two chip configuration requires both parts to have cfg0 tied low and cfg1 tied high. cfg2 is used as a chip select when it matches the value of a26. therefore, one device must have cfg2 tied low and the other device must have cfg2 tied high. 1mb: the four chip configuration requires all four devices to have cfg0 tied high. the cfg1, cfg2 vector becomes the chip select when it matches the a25, a26 vector. therefore, each of the four parts must have a unique value of the cfg[1:2] vector. 5.2.2.cfg3 many core logic chipsets are designed such that the dma bridge and the memory controller are resident in the same device. in su ch systems there is internal communication between these two functional units. bus transactions generated by the dma bridge are solely for the purpose of keeping the system coherent. they are not explicit requests from memory that have data tenures associ ated with them. however, some chipsets are designed with the memory controller and the dma bridge partitioned into different devices . in systems such as these, transactions generated by the dma bridge are true memory requests that have data tenures associated with them. these are called snoop data tenures. because these two types of systems are fundamentally different, the tspc2605 must know in which type of system it is resident in order to respond properly to the different types of transactions. for systems th at do not have snoop data tenures, cfg3 must be tied high. for systems that do use snoop data tenures, cfg3 must be tied low.
tspc2605 14/36 5.2.3.cfg4 when the tspc2605 asserts l2 claim to signal to the memory controller that a cache hit has been detected, it is taking control of the address and data tenures of the transaction (see 60x bus operation and memory coherence ). this means that the tspc2605 will assert aack to end the address tenure, and it will assert ta as needed for the data tenure. if the data bus is idle when a processor request is initiated, the tspc2605 will assert aack the cycle after ts was asserted. if the data bus is busy when the request is made, the tspc2605 will wait until the outstanding data tenure has completed before asserting aack . by holding off on the assertion of aack , the tspc2605 enforces the policy of, at most, two outstanding data transactions at any one time. tying cfg4 low prevents the tspc2605 from asserting aack to end transactions for which it has asserted l2 claim . in systems that tie cfg4 low it is neces- sary for the memory controller to assert aack for all transactions. this allows the dma bridge to initiate snoop transactions (as defined later) even when there are two outstanding data transactions. if this type of system is implemented, the arbiter must e nsure that the processor's bus grant is negated once there are two outstanding data transactions. it is expected that most systems wi ll tie cfg4 high. 5.3. reset/initialization to ensure proper initialization and system functionality, the hreset pin of the tspc2605 should be connected to the same signal that is used to reset the processor. the trst signal must be negated before hreset is negated. when hreset is negated, the tspc2605 commences an internal initialization sequence to clear all of the valid bits in the cache. the sequence takes approxi- mately 4000 clock cycles. during this time the tspc2605 will not participate in any bus transaction that occurs. all transactio ns are, however, monitored so that, regardless of when the initialization sequence completes, the tspc2605 is prepared to take action o n the next transaction initiated by the processor. at some point after this 4000 cycle sequence, the tspc2605 will detect its first cache hit. at this time the system will experi ence its first assertion of l2 claim . if the memory controller must be configured via software to comprehend assertions of l2 claim , this configuration operation must have completed by this time. for systems that cannot guarantee that this requirement is met, it is neces- sary to disable the tspc2605 until such time as this configuration can be guaranteed. disabling the tspc2605 can be accomplishe d by asserting l2 update inh sometime during reset and negating it when it is deemed safe for caching to commence. 5.4. 60x bus operation all transactions have what is called an address tenure. an address tenure is a set number of bus cycles during which the addres s bus and its associated control signals are being used for the transaction at hand. in general, there are two types of transactions. those that only have address tenures, called addressonly transactions. and those that require the use of the data bus and therefore will have a data tenure. these transactions are called data transactions. this section describes how address and data tenures are defined as viewed by the tspc2605. 5.4.1.address tenures address tenures on the 60x bus are fairly well defined. they start with an assertion of ts by a device that has been granted the bus by the system arbiter. this device is called the bus master for this transaction. at the same time that ts is asserted, the bus master also drives the address and all other relevant control signals that define the transaction. ts is only asserted for one cycle but all other signals are held valid by the bus master until some other device asserts aack . the device that asserts aack becomes the slave to this transaction. typically, the slave is the memory controller, although for transactions that are cache hits the tspc2605 bec omes the slave by driving l2 claim . transactions can be aborted by any device on the bus by asserting artry . artry may be asserted at any time after ts is asserted, but must be held through the cycle after aack is asserted. this cycle is referred to as the artry window, since it is the cycle in which all devices sample artry to determine if the address tenure has completed successfully. if an address tenure is not aborted by an assertion of artry , then the next bus master is free to assert ts , the cycle after the artry window to start a new address tenure. if artry is asserted in the artry window, all devices that are not asserting artry must negate their bus request in the following cycle. this next cycle is called the br window. the purpose of this protocol is to gi ve immedi- ate bus mastership to the device that asserted artry with the expectation that that device will take this opportunity to clean up whatever circumstances caused it to assert artry . typically, this involves writing data back to memory to maintain coherence in the system.
tspc2605 15/36 5.4.2.data tenures data tenures are more complicated to define than address tenures. they require two conditions to start: an assertion of ts that initi- ates a data transaction and a qualified assertion of the bus master's data bus grant. for a data bus grant to be considered qua lified, no device on the bus may be asserting dbb in the cycle that the data bus grant is asserted. data transactions come in two types: singlebeat transactions and burst transactions. the type is determined by the state of tb st during the address tenure of the transaction. if the bus master asserts tbst , the transaction is a burst transaction and will require four assertions of ta in order to complete normally. if tbst is negated during the address tenure, the transaction only requires one asser- tion of ta , thus the name singlebeat. which device drives the data bus during a data transaction depends upon whether the transaction is a read or a write. for a rea d transaction, the slave device drives the data bus. for a write transaction, the master drives the data bus. in all data transac tions, the slave device asserts ta to indicate that either valid data is present on the bus, in the case of a read; or that it is reading data off the data bus, in the case of a write. the master device asserts dbb the cycle after it has been granted the data bus and keeps it asserted until the data tenure has completed. a data tenure can be aborted in two different ways. the address tenure for the transaction can be aborted by an assertion of ar try . or, the slave device may assert tea to indicate that some error condition has been detected. either event will prematurely terminate the data tenure. 5.4.3.data streaming for the majority of data transactions there must be a wait state between the completion of one data tenure and the start of the next. this turnaround cycle avoids the contention on the data bus that would occur if one device starts driving data before another d evice has had a chance to turn off its data bus drivers. when a cache read hit is pipelined on top of another cache read hit, there i s no need for this turnaround cycle since the same device will be driving the data bus for both data tenures. the 60x bus has the ability to remove this unnecessary wait state and allow backtoback cache read hits to stream together. this ability is only enabled if the syst em is put into fast l2 mode. note that not all powerpc processors support fast l2 mode. one of the requirements for taking advantage of this data streaming capability is that the system arbiter must be sophisticated enough to identify situations in which streaming may occur. upon recognizing these situations, it must assert the processor's data bus grant in the cycle coincident with the fourth assertion of ta of the first cache read, so that the data tenure for the second cache read may commence in the next cycle. because it only recognizes qualified assertions of cpu dbg , the tspc2605 must not be aware of the processor's assertions of dbb . this means that the dbb pin of the tspc2605 must be tied to a pullup resistor rather than connected to the system dbb to which all other devices are connected. this forces the system arbiter to a level of sophistication such that it only supplies q ualified data bus grants and thus the dbb signal is unnecessary to the whole system. note: in a multichip configuration each tspc2605 device acts as an independent cache. zero wait state data streaming can only occur if the back to back read hits occur in a given device. if the second read hit is not in the device as the first read hit, a wait state will occur between the two data tenures (21112111 timing). 5.4.4.data bus parking the tspc2605 has the ability to respond to a processor read or write hit starting in the cycle after the processor has asserted ts . this is referred to as a 2111 response. however, even though the tspc2605 has this ability, it is dependent upon the system to al low this quick of a response to occur. as discussed above, a data tenure cannot start until the master has been given a qualified b us grant. in order for the data tenure to start the cycle after ts is asserted, the data bus must be granted in the cycle coincident with the asser- tion of ts . at bus speeds of 66 mhz it is extremely difficult for an arbiter to detect an assertion of ts and itself assert cpu dbg in the same cycle. in order to realistically allow this situation to occur, cpu dbg must be asserted independent of the processor's assertion of ts . data bus parking is a system feature whereby the processor always has a qualified data bus grant when the data bus is idle. it is also a requirement for systems which seek to take advantage of the 2111 response time capabilities of the tspc2605. this feature is typically present in arbiters that have the level of sophistication necessary to support data streaming. but it is also a featu re of systems that do not even have a data bus arbiter. in these systems the data bus grant of every device in the system is tied to ground. the assertion of dbb by the current data bus master effectively removes the qualified data bus grant of all devices in the system, including its own. note that in systems that have no data bus arbiter that it is impossible to take advantage of data streaming. there is another caveat associated with data bus parking. care must be taken when using data bus parking along with fast l2 mod e. in normal bus mode when the processor reads data off the bus, it will wait one cycle before passing the data on to internal fun ctional units. the purpose of this one cycle waiting period is to check for an assertion of drtry , which invalidates the data that has been already read. one of the advantages of running the processor in fast l2 mode is that this internal processor wait state is remo ved. a problem will arise, however, if the processor is given data the cycle after ts is asserted, as is possible with the tspc2605, and the transaction is aborted by some other device asserting artry . because the processor will not sample artry until two cycles after the assertion of ts , the data read off the bus will have already been forwarded to theinternal functional units. thus, incorrect results may occur in the system. to avoid this situation in a system that seeks to run fast l2 mode with the data bus parked, there must be a guarantee that art ry will never be asserted for cache read hits. this is a further requirement to be imposed upon the dma bridge and the memory controlle r. if this guarantee cannot be made, the data bus cannot be parked when running in fast l2 mode.
tspc2605 16/36 5.4.5.processor reads when the processor issues a read transaction, the tspc2605 does a tag lookup to determine if this data is inthe cache. if there is a cache hit and ci is not asserted, the tspc2605 will assert l2 claim and supply the data to the processor when the data tenure starts. if the processor issues a cacheinhibited read (ci asserted) and the tspc2605 detects a cache hit to a nondirty, or clean, cache line, the line will be marked invalid. if the cacheinhibited read hits a dirty line, the tspc2605 will assert artry and write the dirty line back to memory. if the read misses in the cache, the tspc2605 will perform a linefill only if it is a burst read and it is not marked cacheinh ibited. during a linefill, the tspc2605 stores the data present on the bus as it is supplied by the memory controller. 5.4.6.processor writes the conditions for asserting l2 claim for processor writes are almost the same as for processor reads. there must be a cache hit and ci must not be asserted. in addition, however, wt must not be asserted. single beat writes that are marked either writethrough or cacheinhibited that hit in the cache cause the tspc2605 to assert artry and write the dirty line back to memory. 5.4.7.transaction pipelining as explained in pipeline depth , the tspc2605 can only handle one level of pipelining on the bus. since the assertion of l2 claim gives it the ability to assert aack , the tspc2605 has the ability to control this pipeline depth for transactions that are cache hits by delaying its assertion of aack . pipelined cache hits are transactions that hit in the cache but occur while there is still an outstanding data transaction on t he bus. the timing of the assertion of aack for a pipelined cache hit is dependent upon the completion of the previous transaction. for explana- tion purposes, the previous transaction will be referred to as transaction one. the pipelined cache hit will be referred to as transaction two. if transaction one is a cache hit, the tspc2605 will be the slave device for the transaction. since, for burst operations, the tspc2605 always asserts ta for four consecutive clock cycles, the end of the data tenure for transaction one will be at a deterministic clock cycle. in this case, aack for transaction two can be asserted coincident with the last assertion of ta for transaction one. if transaction one is not a cache hit, the tspc2605 will wait until after the data tenure for transaction one has completed before asserting a ack to complete the address tenure of transaction two. 5.5. memory coherence when a processor brings data into its onchip cache and modifies it, a situation has arisen in which the main memory now contai ns irrelevant, or stale, data. given that most systems support some form of dma there must exist a means by which the processor is forced to write this modified, or dirty, data back to main memory. the dma bridge is responsible for generating bus transaction s to ensure that main memory locations accessed by dma operations do not contain stale data. these transactions, called snoops, come in three different categories, each of which will be discussed below. snoops cause the processor and the tspc2605 to check to see if they have dirty copies of the memory location specified in the snoop transaction. if either device does have a dirty copy it will assert artry and make use of the opportunity presented in the br window to write this data back to main memory. situations can arise where a cache line is dirty in both the processor's l1 cache and in the tspc2605. in cases such as these, snoop transactions should cause the processor to write its data back to memory since it is by definition more recent than the data in the tspc2605. since artry is a shared signal and it cannot be determined which devices are driving it, the tspc2605 samples cpu br in the br window to determine if the snoop hit a dirty line in the l1 cache. if cpu br is asserted during this window, the tspc2605 will defer to the processor. 5.5.1.snoop reads a snoop read causes dirty data to be written back to memory but allows both the l1 and l2 to keep a valid copy. in cases where the snoop hits a dirty cache line in the processor, the tspc2605 will update its contents as the processor writes the data back to main memory. snoop reads can be implemented in two ways. one is that the dma bridge can issue a clean transaction (tt[0:4] = 00000). the oth er is that the dma bridge can do a read transaction (tt[0:4] = x1010). if the dma bridge does a read transaction, the tspc2605 det er- mines that it is a snoop read rather than a processor read by the state of cpu bg the cycle before ts was asserted. if the processor was not granted the bus then the transaction had to have been issued by the dma bridge and is therefore a snoop read. 5.5.2.snoop writes snoop writes also cause dirty data to be written back to main memory. the difference from a snoop read is that the cache line m ust then be invalidated in both the processor's cache and in the l2 cache. when the processor writes data back to memory in respons e to a snoop write, the tspc2605 will not cache the data as it appears on the bus. if a valid copy resides in the cache, the tspc260 5 will invalidate it. again there are multiple transactions that can be used by the dma bridge to implement a snoop write. it can issue a flush trans action (tt[0:4] = 00100), a read with intent to modify (tt[0:4] = x1110), or a write with flush (tt[0:4] = 00010). as with snoop reads , the tspc2605 distinguishes between processor issued data transactions and snoop transactions by the state of cpu bg in the cycle previous to the assertion of ts .
tspc2605 17/36 5.5.3.snoop kills kills are snoops that cause cache entries to be immediately invalidated, regardless of whether they are dirty. this saves time if the dma operation is going to modify all the data in the cache line. to implement a snoop kill the dma bridge can issue a kill tran saction (tt[0:4] = 01100) or a write with kill (tt[0:4] = 00110). 5.6. two/four chip implementation 5.6.1.multiple castouts because each tspc2605 has its own castout buffer (cob), it is possible for situations to arise in which more than one device ne eds to do a copyback operation. under normal circumstances each device will enter castout conditions at different times. in these c ases, when a device determines that it needs to do a castout, the l2 br signal is first sampled. if l2 br is already asserted then it is clear that another device is also in a castout situation. the late device will wait until l2 br is negated before continuing in its attempt to perform its castout. because of the br window protocol associated with assertions of artry , it is possible for a situation to arise where device two is waiting for device one to do its castout before asserting l2 br . if there is an assertion of artry by a device other than device one, device one is required to negate l2 br in the br window. in order to prevent device two from interpreting device one's negation of l2 br as an indication that device one has completed its castout, a simple arbitration mechanism is used. all devices have a simple twobit counter that is synchronized such that all counters always have the same value. for the purposes of performing a castou t operation, a given pair can only assert l2 br if the counter is equal to its value of cfg[1:2]. this simple mechanism prevents more than one device from asserting l2 br in the same cycle and therefore not being cognizant of the another device's need to perform a castout. 5.6.2.snoop hit before castout the other situation that can cause problems with a shared bus request occurs when a snoop hits a dirty line in one of the tspc2 605 devices. if device one has a cache line in its cob, it will assert l2 br so that it may perform a castout operation. if a snoop hits a dirty line in device two, it will assert both artry and l2 br so that it can write the snoop data back to main memory. when device one detects that artry has been asserted, it needs to be made aware that device two needs to request the bus. otherwise, at the same time that device two is asserting l2 br , device one will attempt to conform to the br window protocol and negate l2 br . this situa- tion is avoided by device one sampling fdn when it detects that artry has been asserted. if fdn is asserted at the same time as artry is asserted, device one will recognize that device two is asserting artry . device one will then highz l2 br so that there will not be contention when device two is asserting l2 br . 5.7. multiprocessing the tspc2605 can be used as a common cache for up to four processors. for each processor there is a bus request, bus grant, and data bus grant signal pin on the tspc2605. each of these pins needs to be connected to the respective processor's arbitration s ig- nals in the system. the tspc2605 treats multiple processors as one processor. thus, the same restrictions on pipelining depth are true with regard to how many processor transactions can be outstanding at any one time. there can only be one data transaction from any processor pipelined on top of a current data transaction that was issued by any processor. the data tenures for all processors must be performed in the same order as the address tenures on a systemwide basis. if proce ssor one makes a request and then processor two makes a request, processor one's data tenure must precede processor two's data tenure. note that this is not a 60x bus restriction, but rather a restriction necessary for proper operation of the tspc2605. the tspc2605 keeps coherent with the l1 caches of multiple processors as defined by the mesi (modifiedexclusivesharedin- valid) protocol without actually implementing the protocol. this is possible for two reasons. since the tspc2605 is a lookasid e cache, all transactions are monitored by all devices on the bus. also, the tspc2605 cannot, on its own, modify data. thus, if o ne processor requests exclusive access to a cache line, it is not necessary for the tspc2605 to invalidate its copy of the data, a s would be required under the mesi protocol. if a second processor requests the same data, the transaction will cause the first process or to assert artry . this will prevent the tspc2605 from supplying stale data to the second processor. as discussed in data bus parking , care must be taken when parking the data bus in fast l2 mode. by the nature of mp systems running under the mesi protocol there will be assertions of artry to abort cache read hits. thus, in an mp system, the data bus cannot be parked to any processor if the system is to be run in fast l2 mode. 5.8. poweringdown an assertion of pwrdn will cause the tspc2605 to go into a lowpower sleep state. this state is entered after pwrdn is synchro- nized and both the address and data buses are idle. all data is retained while in the sleep state. the behavior of the tspc2605 upon negation of pwrdn is dependent upon the state of wt at the rising edge of hreset . if wt is asserted at reset, the tspc2605 will invalidate all cache entries when pwrdn is negated. if wt is negated at reset, the tspc2605 will leave all cache entries as they were prior to the assertion of pwrdn . however, in this situation, the system designer must insure that no bus activity occur within two microseconds of the negation of pwrdn . note: while in the sleep state the tspc2605 does not disable its internal clock network. the low power state current stated in this specification assumes that the system clock is not toggling.
tspc2605 18/36 5.9. asynchronous signals the tspc2605 supports four asynchronous control signals. these signals were originally defined in the powerpc reference plat- form (prep) specification. because these signals are defined to be asynchronous, the tspc2605 must synchronize them internally. this process takes eight clock cycles. thus, to guarantee recognition by the tspc2605, assertions of any one of these signals m ust last a minimum of eight clock cycles. 5.9.1.l2 flush when l2 flush is asserted, the tspc2605 initiates an internal sequence that steps through every cache line present. valid lines that are clean are immediately marked invalid. valid lines that are dirty must be written back to main memory. to keep memory up to date, the tspc2605 must still monitor all transactions on the bus. any transaction that is not a processor burst write will cause the tspc2605 to assert artry . burst writes cause the tspc2605 to do a lookup on the affected address and mark the line invalid if it is present. because the tspc2605 must still monitor all transactions, it cannot use the tag ram for the flush sequence unless there is a gu aran- tee that no new transaction will be initiated on the bus. the only way to ensure that no new transactions will occur is for the tspc2605 to be granted the bus. thus, upon entering the sequence initiated by the assertion of l2 flush , the tspc2605 will assert l2 br . as soon as l2 bg is asserted, the tspc2605 can start stepping through the tag ram entries. l2 flush need not be held asserted for the flush sequence to complete. once started the sequence will run to completion unless overridden by an assertion of hreset . 5.9.2.l2 miss inh when l2 miss inh is asserted, the tspc2605 will not load any new data into the cache. the data already present will remain valid and the tspc2605 will respond to cache hits. this condition only lasts as long as l2 miss inh is asserted. when l2 miss inh is negated, the tspc2605 will start to bring new data into the cache when there are cache misses. 5.9.3.l2 tag clr when l2 tag clr is asserted, the tspc2605 will invalidate all entries in the cache. this internal sequence is the same as the one initiated by an assertion of hreset . during this sequence, the tspc2605 will not participate in any bus transaction. however, it will keep track of all bus transactions so that when the sequence is finished, the tspc2605 can immediately participate in the next bus transaction. as is the case with assertions of l2 flush , an assertion of l2 tag clr need not be held for the duration of the sequence. once asserted the sequence will run to completion regardless of the state of l2 tag clr . 5.9.4.l2 update inh when l2 update inh is asserted, the tspc2605 is disabled from responding to cacheable transactions. bus transactions continue to be monitored so that as soon as l2 update inh is negated, the mpc204ga can participate in the next transaction.
tspc2605 19/36 5.10. waveforms 5.10.1.read hit/write hit figure 1 shows a read hit from an idle bus state. the tspc2605 asserts l2 claim the cycle after ts to inform the memory controller that there is a cache hit and the cache will control the rest of the transaction. l2 claim is held through the cycle after aack is asserted. since there are no active data tenures from previous transactions, the tspc2605 asserts aack the cycle after ts is asserted. note there must be a qualified assertion of cpu dbg in the same cycle as the assertion of ts for the tspc2605 to respond with ta in the next cycle. cpu dbg does not affect the timing of l2 claim or aack . the write hit timing is virtually the same. the only difference is the processor drives the data instead of the tspc2605. clk cpu bg ts a0 a31 tbst l2 claim aack cpu dbg dbb ta dh0 dh31, dl0 dl31 12 34 56 a a1 a2 a3 a4 signal driven to the tspc2605 signal driven by the tspc2605 highz legend figure 1. burst read (or write) hit
tspc2605 20/36 5.10.2.multiple read/write hits (normal bus mode) figure 2 is an illustration of tspc2605 pipeline depth limit with multiple read hits. the tspc2605 supports only one level of a ddress pipelining for data transfer. therefore, it must hold off on its assertion of aack for a pipelined ts until the data tenure for the first ts is done. the tspc2605 asserts aack at the same time as the fourth ta for data tenures that it controls. clk cpu bg ts a0 a31 tbst l2 claim aack cpu dbg dbb ta dh0 dh31, dl0 dl31 12 34 5 6 7 8 91011 ab c a1 a2 a3 a4 b1 b2 b3 b4 signal driven to the tspc2605 signal driven by the tspc2605 highz legend figure 2. multiple burst read (or write) hits
tspc2605 21/36 5.10.3.read miss (normal bus mode) figure 3 is an illustration of tspc2605 pipeline depth with a read miss followed by a read hit. for illustration purposes the read miss is shown as a 3111 response from memory. aack for the second access is not driven true until the cycle after the fourth ta of the read miss. this is because the tspc2605 is not in control of ta for the first access and must, therefore, wait until the first access' data tenure is complete before it can drive aack true for the read hit. cpu bg ts a0 a31 tbs t l2 claim aac k cpu dbg dbb ta dh0 dh31, dl0 dl31 cl k 1234 56 78 9101112 ab a1 a2 a3 a4 b1 b2 b3 b4 signal driven to the tspc2605 signal driven by the tspc2605 highz legend figure 3. read miss followed by a burst read hit for mpc603/604
tspc2605 22/36 5.10.4.multiple read hits (fast l2 mode) back to back pipelined burst read hits for the mpc604 in fast l2 mode, also called data streaming mode, are shown in figure 4. note that cpu dbg is negated except for the cycles coincident with the fourth ta of each data tenure. this is a requirement for data streaming. note also that dbb is not shown. for proper operation in fast l2 mode the dbb pin of the tspc2605 must be tied to a pullup resistor. clk cpu bg ts a0 a31 tbst l2 claim aack cpu dbg ta dh0 dh31, dl0 dl31 12345 6789101112 ab c d a1 a2 a3 a4 b1 b2 b3 b4 c1 c2 c3 signal driven to the tspc2605 signal driven by the tspc2605 highz legend figure 4. multiple burst read hits in fast l2 mode
tspc2605 23/36 5.10.5.write through burst write hit figure 5 shows the fastest possible burst write hit to a writethrough mode l2 cache line, read miss or write miss processing t hat replaces a clean line. for these operations tspc2605 will not assert any signals on the 60x bus. a cache line is considered wri te through if wt is asserted by the processor when it asserts ts . the speed at which a writethrough operation completes is solely dependent on the memory controller. the timing shown here assumes that the memory controller has a write buffer that can accept data this quickly. clk cpu bg ts a0 a31 wt l2 claim aack cpu dbg dbb ta dh0 dh31, dl0 dl31 1 2 345 6 a1 78 a a2 a3 a4 tbs t signal driven to the tspc2605 signal driven by the tspc2605 highz legend figure 5. fastest possible write through burst write hit for mpc603/604
tspc2605 24/36 5.10.6.read/write miss figure 6 is an illustration of a processor read or write miss that causes the tspc2605 to replace a dirty line. l2 br is asserted two clocks after ts . the dirty data to be replaced is moved into the internal cast out buffer (cob) at the same time the new data is written into the cache. note that the copyback operation occurs after the processor request is satisfied. in addition, no delay is adde d to the processor transaction. it proceeds as fast as the memory controller will allow. clk cpu bg l2 br l2 bg ts a0 a31 tbs t l2 claim aack cpu dbg l2 dbg dbb ta dh0 dh31, dl0 dl31 123456789101112 ab a1 a2 a3 a4 b1 b2 b3 b4 signal driven to the tspc2605 signal driven by the tspc2605 highz legend figure 6. read or write miss followed by castout
tspc2605 25/36 5.10.7.read/write snoop hit (dirty l2 line) figure 7 is an illustration of a read or write snoop to a cache line that is dirty in the l2, but is not dirty in the processor 's cache. when a snoop hits a dirty line, the tspc2605 will assert artry through the cycle following the assertion of aack . this cycle is called the artry window. note that the tspc2605 also asserts l2 br at the same time it asserts artry . because the snoop could also have hit a dirty line in the processor's cache, the tspc2605 samples the processor's br signal the cycle following the artry window. this cycle is called the br window. if the processor's br signal is not asserted, the tspc2605 will start sampling l2 bg , the cycle after the br window. note that the tspc2605 cannot do a 2111 copy back burst. the earliest that it can handle the first assertion of ta is two cycles after its assertion of ts . clk cpu br l2 br l2 bg ts a0 a31 l2 claim aack cpu dbg l2 dbg dbb ta dh0 dh31, dl0 dl31 cpu bg aaa artry a1 a2 a3 a4 123456789101112 signal driven to the tspc2605 signal driven by the tspc2605 highz legend figure 7. read or write snoop hit to dirty l2 cache line and clean processor cache line
tspc2605 26/36 5.10.8.read/write snoop hit (dirty l2 and processor line) an illustration of powerpc read or write snoop hit to a dirty l2 cache line is shown in figure 8. the processor has a dirty cop y of the cache line. in this case, both the processor and the tspc2605 assert artry . this situation is detected by sampling cpu br in the br window, as described in the previous example. if cpu br is asserted in the br window, the tspc2605 will negate l2 br . it will also ignore assertions of l2 bg . this allows the processor to write back its dirty cache line, at which time the tspc2605 will either update or invalidate its copy depending on whether it is a snoop read or snoop write. 123456789101112131 4 a1 a2 a3 a4 a a a clk cpu br l2 br l2 bg ts a0 a31 l2 claim aack cpu dbg l2 dbg dbb ta dh0 dh31, dl0 dl31 cpu bg artry signal driven to the tspc2605 signal driven by the tspc2605 highz legend figure 8. read or write snoop hit to dirty l2 cache line and dirty processor cache line
tspc2605 27/36 5.10.9.read hit/write hit (without cpu dbg parked) most of the previous examples have assumed cpu dbg is asserted in the same cycle that the processor asserts ts . this implies cpu dbg is parked. in some systems it may not be desirable or possible to park cpu dbg . figure 9 shows the response for a read hit from the tspc2605 is gated by the assertion of cpu dbg . the fastest response possible in a system that does not park cpu dbg is 3111. 1234 56 7 a a1 a2 a3 a4 cl k ts a0 a31 tbs t l2 claim aac k db b ta dh0 dh31, dl0 dl31 cpu bg cpu dbg signal driven to the tspc2605 signal driven by the tspc2605 highz legend figure 9. burst read (or write) hit without cpu dbg parked
tspc2605 28/36 5.11. test access port description 5.11.1.instruction set a five pin ieee standard 1149.1 test port (jtag) is included on this device. when the tap (test access port) controller is in t he shiftir state, the instruction register is placed between tdi and tdo. in this state, the desired instruction would be seriall y loaded through the tdi input. trst resets the tap controller to the testlogic reset state. the tap instruction set for this device ar e as follows. 5.11.2.standard instructions instruction code (binary) description bypass 1111* bypass instruction sample/preload 0010 sample and/or preload instruction extest 0000 extest instruction highz 1001 highz all output pins while bypass register is between tdi and tdo clamp 1100 clamp output pins while bypass register is between tdi and tdo * default state at powerup. 5.11.3.sample/preload tap instruction the sample/preload tap instruction is used to allow scanning of the boundaryscan register without causing interference to the normal operation of the chip logic. the 169bit boundaryscan register contains bits for all device signal and clock pins and associated control signals. this register is accessible when the sample/preload tap instruction is loaded into the tap instruc- tion register in the shiftir state. when the tap controller is then moved to the shiftdr state, the boundaryscan register is placed between tdi and tdo. this scan register can then be used prior to the extest instruction to preload the output pins with desired values so that these pins will drive the desired state when the extest instruction is loaded. as data is written into t di, data also streams out tdo which can be used to presample the inputs and outputs. sample/preload would also be used prior to the clamp instruction to preload the values on the output pins that will be driven o ut when the clamp instruction is loaded. 5.11.4.extest tap instruction the extest instruction is intended to be used in conjunction with the sample/preload instruction to assist in testing board lev el connectivity. normally, the sample/preload instruction would be used to preload all output pins. the extest instruction would then be loaded. during extest, the boundaryscan register is placed between tdi and tdo in the shiftdr state of the tap controller. once the extest instruction is loaded, the tap controller would then be moved to the runtest/idle state. in this s tate, one cycle of tck would cause the preloaded data on the output pins to be driven while the values on the input pins would be sampled . note the tck, not the clock pin (clk), is used as the clock input while clk is only sampled during extest. after one clock cycl e of tck, the tap controller would then be moved to the shiftdr state where the sampled values would be shifted out of tdo (and new values would be shifted in tdi). these values would normally be compared to expected values to test for board connectivity. 5.11.5.clamp tap instruction the clamp instruction is provided to allow the state of the signals driven from the output pins to be determined from the bound ary scan register while the bypass register is selected as the serial path between tdi and tdo. the signals driven from the output pins will not change while the clamp instruction is selected. extest could also be used for this purpose, but clamp shortens the boa rd scan path by inserting only the bypass register between tdi and tdo. to use clamp, the sample/preload instruction would be used first to scan in the values that will be driven on the output pins when the clamp instruction is active. 5.11.6.highz tap instruction the highz instruction is provided to allow all the outputs to be placed in an inactive drive state (highz). during the highz instruc- tion the bypass register is connected between tdi and tdo. 5.11.7.bypass tap instruction the bypass instruction is the default instruction loaded at power up. this instruction will place a single shift register betwe en tdi and tdo during the shiftdr state of the tap controller. this allows the board level scan path to be shortened to facilitate testin g of other devices in the scan path.
tspc2605 29/36 5.11.8.disabling the test access port and boundary scan it is possible to use this device without utilizing the four pins used for the test access port. to circuit disable the device, tck must be tied to v ss to preclude mid level inputs. trst should be tied to v ss to ensure proper hreset operation. although tdi and tms are designed in such a way that an undriven input will produce a response equivalent to the application of a logic 1, it is still a dvisable to tie these inputs to v dd through a 1k resistor. tdo should remain unconnected. shiftdr exit1ir select ir scan pauseir testlogic reset exit1dr updateir captureir shiftir exit2ir 0 runtest/ idle 1 updatedr exit2dr pause 1dr capturedr 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 select dr scan 0 note: the value adjacent to each state transition represents the signal present at tms at the rising edge of tck. figure 10. tap controller state diagram
tspc2605 30/36 5.12.boundary scan order 5.12.1.bit number the order of the boundary scan chain. bit 0 is the closest to tdo. 5.12.2.bit/pin name the name of the physical pin. for an output enable cell, this is the name of the corresponding output enable. 5.12.3.bit/pin type input e input only pin. i/o e bidirectional pin that can be put into highz state. output e output only pin. output enable e boundary scan cell to hold the output enable state of other i/o pads. output enable does not correspond to a physical pin. to set an i/o to an input, the output enable must have a 1. to set an i/o to an output, the output enable must ha ve a 0. note that these internal output enables are active low. reserved this signal is reserved and must always be a 1. 5.12.4.output enable the name of the output enable cell that determines if the cell is enabled or in the highz state. if the pin type is input or o utput enable, this entry will be empty. bit number bit/pin name bit/pin type output enable 0 reserved reserved 1 dl16 i/o doe 2 dl17 i/o doe 3 dl18 i/o doe 4 dl19 i/o doe 5 dl20 i/o doe 6 dl21 i/o doe 7 dl22 i/o doe 8 dl23 i/o doe 9 dp6 i/o doe 10 dl24 i/o doe 11 dl25 i/o doe 12 dl26 i/o doe 13 dl27 i/o doe 14 dl28 i/o doe 15 dl29 i/o doe 16 dl30 i/o doe 17 dl31 i/o doe 18 dp7 i/o doe 19 dh24 i/o doe 20 dh25 i/o doe 21 dh26 i/o doe 22 dh27 i/o doe 23 dh28 i/o doe 24 dh29 i/o doe 25 dh30 i/o doe 26 dh31 i/o doe bit number bit/pin name bit/pin type output enable 27 dp3 i/o doe 28 dh16 i/o doe 29 dh17 i/o doe 30 dh18 i/o doe 31 dh19 i/o doe 32 dh20 i/o doe 33 dh21 i/o doe 34 dh22 i/o doe 35 dh23 i/o doe 36 dp2 i/o doe 37 l2 bg input 38 l2 miss inh input 39 abb i/o abboe 40 cpu3 dbg input 41 cpu3 bg input 42 cpu3 br input 43 cpu2 dbg input 44 cpu2 bg input 45 cpu2 br input 46 fdn i/o fdnoe 47 l2 dbg input 48 l2 br i/o l2broe 49 ta i/o taoe 50 l2 claim output l2claimoe 51 cpu dbg input 52 aack i/o aackoe 53 ci i/o aoe
tspc2605 31/36 bit number bit/pin name bit/pin type output enable 54 artry i/o artryoe 55 wt i/o aoe 56 cpu br input 57 tea input 58 pwrdn input 59 dbb i/o dbboe 60 hreset input 61 tbst i/o aoe 62 tt0 i/o aoe 63 ts i/o aoe 64 tt1 i/o aoe 65 tt2 i/o aoe 66 tt4 i/o aoe 67 tt3 i/o aoe 68 cpu bg input 69 sreset input 70 l2 tag clr input 71 l2 update inh input 72 cpu4 bg input 73 cpu4 dbg input 74 cpu4 br input 75 cfg0 input 76 cfg2 input 77 cfg1 input 79 dh8 i/o doe 79 dh9 i/o doe 80 dh10 i/o doe 81 dh11 i/o doe 82 dh12 i/o doe 83 dh13 i/o doe 84 dh14 i/o doe 85 dh15 i/o doe 86 dp1 i/o doe 87 dh0 i/o doe 88 dh1 i/o doe 89 dh2 i/o doe 90 dh3 i/o doe 91 dh4 i/o doe 92 dh5 i/o doe 93 dh6 i/o doe 94 dh7 i/o doe 95 dp0 i/o doe 96 dl0 i/o doe bit number bit/pin name bit/pin type output enable 97 dl1 i/o doe 98 dl2 i/o doe 99 dl3 i/o doe 100 dl4 i/o doe 101 dl5 i/o doe 102 dl6 i/o doe 103 dl7 i/o doe 104 dp4 i/o doe 105 dl8 i/o doe 106 dl9 i/o doe 107 dl10 i/o doe 108 dl11 i/o doe 109 dl12 i/o doe 110 dl13 i/o doe 111 dl14 i/o doe 112 dl15 i/o doe 113 dp5 i/o doe 114 a0 i/o aoe 115 a1 i/o aoe 116 a2 i/o aoe 117 a3 i/o aoe 118 a4 i/o aoe 119 a5 i/o aoe 120 a6 i/o aoe 121 a7 i/o aoe 122 a8 i/o aoe 123 a9 i/o aoe 124 a10 i/o aoe 125 a11 i/o aoe 126 a12 i/o aoe 127 a31 i/o aoe 128 a30 i/o aoe 129 a29 i/o aoe 130 a28 i/o aoe 131 a27 i/o aoe 132 a26 i/o aoe 133 a25 i/o aoe 134 a24 i/o aoe 135 a23 i/o aoe 136 a22 i/o aoe 137 a21 i/o aoe 138 a20 i/o aoe 139 a19 i/o aoe
tspc2605 32/36 bit number bit/pin name bit/pin type output enable 140 a18 i/o aoe 141 a17 i/o aoe 142 a16 i/o aoe 143 a15 i/o aoe 144 a14 i/o aoe 145 a13 i/o aoe 146 tsiz2 i/o aoe 147 tsiz0 i/o aoe 148 tsiz1 i/o aoe 149 gbl output aoe 150 cfg3 input 151 l2 ci input 152 l2 flush input 153 ap0 i/o aoe 154 ap1 i/o aoe 155 ap2 i/o aoe 156 ap3 i/o aoe 157 ape output apeoe 158 taoe output enable 159 l2claimoe output enable 160 l2broe output enable
tspc2605 33/36 6. preparation for delivery 6.1. packaging microcircuits are prepared for delivery in accordance with mil-prf-38535. 6.2. certificate of compliance tcs offers a certificate of compliances with each shipment of parts, affirming the products are in compliance either with mil-s td-883 and guarantying the parameters not tested at temperature extremes for the entire temperature range. 7. handling mos devices must be handled with certain precautions to avoid damage due to accumulation of static charge. input protection dev i- ces have been designed in the chip to minimize the effect of this static buildup. however, the following handling practices are recom- mended : a) devices should be handled on benches with conductive and grounded surfaces. b) ground test equipment, tools and operator. c) do not handle devices by the leads. d) store devices in conductive foam or carriers. e) avoid use of plastic, rubber, or silk in mos areas. f) maintain relative humidity above 50 percent if practical.
tspc2605 34/36 8. package mechanical data 8.1. 241 pins pbga package dimensions zp package pbga case 113801 dim min max millimeters a 2.05 a1 0.50 0.70 a2 0.95 1.35 a3 0.70 0.90 b 0.60 0.90 d 25.00 bsc d1 22.86 bsc d2 22.40 22.60 e 25.00 bsc e1 22.86 bsc e2 e 1.27 bsc notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension b is the solder ball diameter measured parallel to datum c. d 0.20 a e e1 0.25 c 0.20 c d2 top view e2 a2 a1 bottom view a3 b 18x 4x d1 e 241 b 12345678910111213141516 a b c d e f g h j k l m n p r t 0.03 c a b 0.15 c a 0.35 c c side view 22.40 22.60 19 18 17 u v w m m
tspc2605 35/36 8.2. 241 pins cbga (to be confirmed) 1.27 bsc package dimensions g package cbga dim min max millimeters a 2.524 3.004 a2 1.37 1.63 a3 2.26 2.70 b 0.76 0.96 d 25.00 bsc d1 22.86 bsc d2 16.3 16.7 e 25.00 bsc e1 22.86 bsc e2 e notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. d e e1 d2 top view e2 a2 bottom view a3 18x d1 e 241 b 12345678910111213141516 a b c d e f g h j k l m n p r t a side view 16.3 16.7 19 18 17 u v w
tspc2605 36/36 9. ordering information tcs prefix (1) temperature range : tc screening leve l (2) : package : ts pc2605 m g 66 m : 55, +125 c v : 40, +110 c b / c zp : pbga g : cbga speed (2) 66 : 66 mhz (1) thomson-csf semiconducteurs specifiques (2) for availability of the different versions, contact your tcs sale office __ : standard b/c : mil-std-883, class b b/t : according to mil-std-883 u : upscreening u/t : upscreening + burn-in (x) type prototype information furnished is believed to be accurate and reliable. however thomson-csf semiconducteurs specifiques assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights o f third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of t hom- son-csf semiconducteurs specifiques. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. thomson-csf semiconducteurs specifi- ques products are not authorized for use as critical components in life support devices or systems without express written appr oval from thomson-csf semiconducteurs specifiques. the powerpc names and logo type are trademarks of international business machines corporation, used under licence ? 1997 thomson-csf semiconducteurs specifiques - printed in france - all rights reserved. this product is manufactured and commercialized by thomson-csf semiconducteurs specifiques - avenue de roche- plaine po box 123 - 38521 saint-egreve cedex - france. for further information please contact : thomson-csf semiconducteurs specifiques - route dpartementale 128 - po box 46 - 91401 orsay cedex - france - phone +33 (0)1 69 33 00 00 - fax +33 (0)1 69 33 03 21 - telex 616780 f tcs - email : lafrique@tcs.thomson.fr

▲Up To Search▲

Price & Availability of TSPC2605VG66

	To Download TSPC2605VG66 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .